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CLAIM CONSTRUCTION ORDER FOR THE FARMWALD/HOROWITZ PATENTS AND ORDER DENYING THE MANUFACTURERS’ MOTIONS FOR SUMMARY JUDGMENT OF NON-INFRINGEMENT AND INVALIDITY DEPENDING ON CLAIM CONSTRUCTION RONALD M. WHYTE, District Judge. Rambus has accused the Manufacturers of infringing various patents. Largely in accord with the local rules, the parties have submitted their joint claim construction statement showing 72 claim terms in dispute. Rambus has filed its opening and responding Markman briefs, motions for summary judgment of infringement, and oppositions to the Manufacturers’ motions. The Manufacturers have filed their responsive Markman brief, oppositions to Rambus’s summary judgment motions, and their own motions for summary judgment of invalidity under Rambus’s proposed claim constructions and non-infringement under theirs. The court has reviewed the papers and considered the arguments of counsel and now sets forth its claim construction and rulings on the summary judgment motions dealing with the Farmwald/Horowitz patents. The claim construction pertaining to the Ware patents is set forth in a separate order. I. THE FARMWALD/HOROWITZ PATENT FAMILY Fifteen of the seventeen patents-in-suit descend from the original patent application no. 07/510,898 filed by Drs. Michael Farmwald and Mark Horowitz on April 18, 1990. Because these fifteen share substantially similar specifications, the court’s discussion refers to U.S. Patent No. 6, 182, 184. Given the number of claim terms in dispute and complexity of the technology, the court begins by explaining the context of the invention and the contents of the specification relevant to the disputed issues. Cf. Phillips v. AWH Corp., 415 F.3d 1303, 1313, 1315-17 (Fed.Cir.2005) (en banc). It then briefly recounts aspects of the prosecution history before turning to claim construction. A. Background of the Inventions and the Specification’s Written Description Drs. Farmwald and Horowitz began their collaboration in the fall of 1988. Tr. 4078:21-4079:7. Dr. Farmwald met with Dr. Horowitz over dinner to discuss how processor speeds and memory speeds were diverging and how memory systems needed to become faster to keep up. Tr. 4079:9-4082:9. Within the semiconductor industry, this problem was commonly referred to as the “memory bottleneck” or “memory gap.” Tr. 4084:7-4091:8 (Dr. Horowitz); 4161:10-4163:3 (Carl Everett); 5498:9-5502:8 (Dr. Farmwald). Over the course of the next year and a half, Drs. Farmwald and Horowitz worked on a variety of ideas for closing the memory gap, and they eventually wrote up their ideas in a patent application. Tr. 4133:15-4134:14. Dr. Horowitz testified that he “took over” the drafting of the specification. Id. The following discussion walks through the patents’ common specification to illustrate the scope of the written description and explain the technology. 1. The Prior Art and Objects of the Invention Dr. Horowitz testified that with the specification, he and Dr. Farmwald were “trying to describe our inventions, all the innovations that we had come up with to build a very high speed interface.” Tr. 4134:10-14. The court will summarize here, however, only the intrinsic evidence and not the inventors’ self-serving testimony. The specification begins with the field of the invention, where it describes “an integrated circuit bus interface” as well as “a new method for physically implementing the bus architecture.” '184 patent, col. 1,11. 21-26. From these introductory sentences, it is clear that the Farmwald/Horo-witz specification discloses more than one invention. The background of the invention discusses general features of prior art memory devices, focusing on how prior art bus architectures were not as efficient as they could be. Id., col. 1, 1. 30-col. 2, 1. 5. The comparison with the prior art is extensive and illustrates some of the problems that Drs. Farmwald and Horowitz sought to address with their inventions. It starts by noting that “prior art memory systems have attempted to solve the problems of high speed access to memory with limited success.” Id, col. 2, 11. 8-10. The first piece of prior art examined by the specification is “the earliest 4-bit micro processor.” Id., col. 2, 11. 10-11 (citing U.S. Pat. No. 3,821,715 (Hoff et. al.)). The Hoff micro processor connected multiple memory devices to a single CPU over a 4-bit wide bus that multiplexed, i.e., carried both, address and control information. Id., col. 2, 11. 13-16. It also used point-to-point control signals to select which memory device the CPU sought to access. Id. Drs. Farmwald and Horowitz critiqued aspects of the Hoff micro processor, noting that it used fixed access times for transmitting information and did not permit the memory devices to send information in blocks. Id., col. 2,11. 16-20. “Most importantly],” its use of point-to-point device select lines meant that it did not send device control information over the bus. Id. The next piece of prior art discussed is U.S. Patent No. 4,315,308 (Jackson), which described a bus architecture using a single 16-bit wide bus that multiplexed data, address, and control information. Id., col. 2, 11. 21-24. It implemented some block-mode operations and allowed some access time variation, but it could not handle multiple requests and did not bus all signals. Id., col. 2, 11. 24-30. Another patent described a DRAM with multiplexed address and data information inside the DRAM, but with a “conventional” bus comprised of separate data, address, and control lines to connect to the external device environment. Id., col. 2,11. 31-34. Shifting away from describing prior art bus architectures, Drs. Farmwald and Horowitz described prior art packaging technology. Id., col. 2, 11. 35-42. While others had attempted to use 3-D packages for DRAMS with connections along a single edge only, the need for point-to-point wiring to enable a master device to select the correct memory device posed complex geometrical problems. Id. No prior art packaging solution had considered using a new interface to do away with the need for point-to-point device select wiring. Leaving DRAM packaging and returning to DRAM architecture, Drs. Farmwald and Horowitz discussed the “state-of-the-art DRAM interface” in U.S. Patent No. 3,969,706 (Proebsting, et.al.). This DRAM architecture used two-way multiplexed address signals and maintained separate pins for data and control information. Id., col. 2, 11. 43-47. One of its problems was that it required more and more pins as the DRAM grew, and many of these pins had to be connected point-to-point to various devices. Id., col. 2,11. 47-50. As previously discussed, this interface complexity made using a 3-D package difficult. The specification next discusses back-plane buses, i.e., the circuit boards used for connecting multiple devices to each other. Some prior art backplane buses had multiplexed address and data information, others used relatively low-voltage signals, and some others used programmable registers and block mode operations. Id., col. 2,11. 51-60. While all backplane buses used some arbitration scheme for prioritizing signals, none used the bus arbitration scheme devised by Drs. Farmwald and Horowitz. Id., col. 2, 1. 61-col. 3, 1. 2. Furthermore, all prior art buses used some point-to-point connections. Id., col. 3,11. 2-4. Finally, the specification summarizes some prior art related to clocking a DRAM interface. Id., col. 3,11. 8-21. Drs. Farm-wald and Horowitz noted that “the clocking scheme used in this invention has not been used before and in fact would be difficult to implement in backplane buses due to the signal degradation caused by connector stubs.” Id., col. 3, 11. 8-11. While a prior art patent had described a clocking scheme using two clock signals, it relied on unusual ramp-shaped clocking signals in lieu of the conventional square signals used by Drs. Farmwald and Horowitz. Id., col. 3,11.11-14. After having surveyed various aspects of the prior art, the specification sets out seven “objects of the invention.” See id., col. 3, 11. 22-48. First, the invention uses “a new bus interface built into semiconductor devices to support high-speed access to large blocks of data from a single memory device by an external user of the data, such as a microprocessor, in an efficient and cost-effective manner.” Id., col. 3, 11. 22-26. Though the invention seeks to address six other objectives, Rambus acknowledges that the “primary object that’s accomplish by the claims at issue is the very first one, which is the new bus interface built into semiconductor devices to support high-speed access to large blocks of data from a single memory device.” Claim Construction Hrg. Tr. 114:7-20 (June 4, 2008). The invention’s second objective is “to provide a clocking scheme to permit high speed clock signals to be sent along the bus with minimal clock skew between devices.” Id., col. 3, 11. 27-29. The invention also seeks to provide a method for mapping out defective devices, distinguishing identical devices connected to the bus, and assigning unique identifiers to otherwise-identical devices. Id., col. 3, 11. 30-35. Yet another object of the invention is to allow a device to transfer address, data, and control information over a relatively narrow bus and provide a bus arbitration scheme to allow multiple devices to use the bus simultaneously. Id., col. 3, 11. 36-40. Finally, the invention seeks “to provide devices, especially DRAMs, suitable for use within the bus architecture of this invention.” Id., col. 3, 11. 46-48. 2. The Summary of Invention The summary of invention begins by describing the new bus interface with substantially fewer bus lines, multiplexed address, data and control information, and no point-to-point device select lines because device select information is included in the control signal. Id., col. 3, 11. 51-61. This new bus also includes clock signals and power along with the multiplexed address, data and control signals. Id., col. 4,11.1-2. While the preferred implementation of the bus interface uses 8 bus data lines and an Addressvalid bus line, “persons skilled in the art will recognize that 16 bus data lines or other numbers of bus data lines can be used to implement the teaching of this invention.” Id., col. 4, 11. 5-8. With the new interface, memory devices can use the bus more efficiently by making large block data transfers and simultaneous transactions. Id., col. 4,11.10-20. The summary next notes that the DRAMs that connect to the new bus differ from conventional DRAMs. The new DRAMs use registers to store control information, device information, and whatever else might be appropriate. Id., col. 4,11. 21-26. They also require circuitry for creating an internal device clock to synchronize the devices on the bus. Id., col. 4, 11. 31-33. Finally, the summary of invention explains that the constrained bus environment enables high clock speeds by shortening the necessary length of the bus. Id., col. 4, 11. 35-50. Taken as a whole, these innovations improve DRAM bandwidth while reducing manufacturing costs and power consumption. Id., col. 4,11. 51-55. 3. The Detailed Description The detailed description of the invention begins with an overview of the new technology, then splits into discrete sections addressing various features of the invention. These feature-specific discussions address: device address mapping (eol.7, 1.17), bus (col.8, 1.16), protocol and bus operation (col.8, 1.42), retry format (col.12, 1.1), system configuration/reset (col.14, 1.46), error detection and correction (col.16, 1.20), low-power 3-D packaging (col.17, 1.14), bus electrical description (col.17, I.62), clocking (col.18, 1.62), multiple buses (eol.19, 1.45), device interface (col.21, 1.23), electrical interface — input/output circuitry (col.21, 1.41) and DRAM column access modification (col.23, 1.42). Only some of these discussions bear on the construction and validity of the claims in dispute. a. The Multiplexed Bus Architecture The detailed description starts by noting that “the present invention is designed to provide a high speed, multiplexing bus for communication between processing devices and memory devices and to provide devices adapted for use in the bus system.” Id., col. 5,11. 29-31. The bus has a number of features. First, it is narrow, i.e., it has a relatively small number of bus lines. Id., col. 5, 11. 35-37. Second, it is multiplexed, meaning, it carries substantially all address, data and control information on the same bus data lines. Id., col. 5, 11. 37-45. This obviates the need for device-select lines because device-select information is carried over the bus. Id. The devices connected by the bus include master devices like the CPU and slave devices like a DRAM. Id., col. 6, 11. 12-16. Every semiconductor device, whether master or slave, has a number of programmable registers for storing information, including device identification, device type, and control settings. Id., col. 6, II. 27-52. For example, preferred embodiments of the patent’s semiconductor devices contain access-time registers that store delay times that control when the device can send and receive data. Id., col. 6,11. 32-37. These register settings can be modified when the device is turned on. Id., col. 6,11. 38-52. The specification’s preferred bus architecture has 11 signal lines. Id., col. 8, 11. 17-34. There are eight bus data lines referred to as “BusDataO” through “Bus-Data7” and collectively described as Bus-Data[0:7]. Id., col. 8, 11. 17-28. These data lines provide a multiplexed bus for address, data and control information that is one byte wide. Id., col. 8, 11. 24-25. There are also two clock lines (Clkl and Clk2) and an AddrValid line. Id. These lines serve to synchronize all of the devices on the bus and to indicate whether the information on the bus includes an address request for all slave devices to decode. Id., col. 8, 11. 25-30. Finally, there is an additional line (Resetin, ResetOut) that connects all devices attached to the bus. While the other signal lines on the bus connect to every device in parallel, the Resetin, ResetOut line connects all of the devices in series so that it can program their registers and assign them unique device identification numbers. Id., col. 8, 11. 30-85. b. The Packet Protocol The bus is the sole courier of information between devices on the bus. Id., col. 6, 11. 53-55. This requires a communication protocol. Id., col. 6, 11. 55-60. The specification describes using a packet protocol. Id. It begins when a master device sends a request packet (“a sequence of bytes comprising address and control information”). Id. Every slave device must decode the packet to determine if it must respond to the request packet. Id., col. 6, 11. 62-64. If it does, the slave device begins its internal processes and responds to the request packet by sending or retrieving data after a programmed delay time. Id., col. 6,1. 64-col. 7,1. 4. A preferred embodiment of the protocol begins when a master device sends out a request packet of address and control information onto the bus. Id., col. 8, 11. 59-62. The AddrValid line is activated, which instructs all slave devices to decode the incoming request packet and decide whether the request packet applies to them. Id., col. 8, 1. 66-col. 9, 1. 4. If the packet contains the slave device’s address, the slave device responds by either transmitting data to the master for a read request or receiving data from the master for a write request. Id. This response occurs after a delay time specified in the memory device’s access-time register. Id., col. 9,11. 11-23. Figure 4 shows the preferred embodiment of a request packet. The request packet is nine bits wide, corresponding to the AddrValid bus line plus the eight bus data lines BusData[0:7], and the packet is six bytes long. Id., col. 9, 11. 24-29. The first byte begins with the AddrValid bit equal to 1 to indicate the beginning of a request packet. Id., col. 9, 11. 29-31. The first byte then contains two four-bit fields sent over the bus data lines. Id., col. 9,11. 39-46. The first four bits are known as AccessType[0:3]. Id., col. 9, 11. 39-41. Ac-cessType[0:3] is an “op code” or “operation code” that specifies the type of access for the DRAM to perform. Id. The second four bits, known as Master[0:3], serve to identify the master device sending the request packet. Id., col. 9, 11. 41-46. Briefly, the forty bits of address data in Address[0:35] and Address[36:39] specify the slave device that should perform the requested operation. See id., col. 9,11. 35-38. Finally, the last four bits of the request packet, known as BlockSize[0:3], tell the DRAM the amount of data involved in the requested operation. No actual data is sent or received in the request packet. The request packet simply allows each DRAM on the bus to: (1) recognize the next six bytes as a request packet, (2) understand what operation is requested, (3) recognize the source of the request packet, (4) determine whether the request packet is addressed to it, and (5) determine the amount of data to send or receive in response to the request packet. In the preferred embodiment, Access-Type[0], i.e, the first bit of the four bit AccessType[0:3] field, is a read/write switch. Id., col. 9, 11. 47-56. If Aecess-Type[0] equals 1, the requested operation is a read and the DRAM should access the data in its memory array and output the data to the bus. Id., col. 9, 11. 50-56. If AccessTypefO] equals zero, the requested operation is a write and the DRAM should prepare to receive data from the bus. Id. The other three bits of the AccessType field, AccessType[l:3], could be used to specify the delay time of the DRAM’s response or trigger preprogrammed responses. See id., col. 9, 11. 56-65; col. 11, 11. 19-37. For example, AccessType[3] can be used to tell the DRAM whether to precharge the sense amplifiers in the memory device to an intermediate voltage between zero and one to allow for a faster response to the next request or to save the information already contained in the memory array. See id., col. 10, 11. 15^48; col. 11,1. 37. The BlockSize[0:3] field determines the size of the following data block transfer. Id., col. 11, 11. 38-39. In the preferred embodiment, if BlockSize[0] equals zero, the size of the following data block corresponds to the binary value of Block-Size[l:3], enabling the data block to be 0 to 7 bits long. Id., col. 11, 11. 39-40. If BlockSize[0] equals one, the data block’s length corresponds to the value of 2 to the power of the binary value of BlockSize[l:3], beginning with 2 s, or 8, bits in length. Id., col. 11, 11. 40-41. Hence, a Block-Size[0:3] equal to 0001 corresponds to a data block that is one bit long. By contrast, a BlockSize[0:3] equal to 1111 corresponds to a data block that is 1,024 bits long, i.e., 2. See id., col. 11, 11. 48-57. These interpretations of BlockSize[0:3] are only illustrative; other encoding schemes are possible simply by changing the meaning of the field’s values. Once the DRAM has decoded the request packet, it must wait the programmed delay time. Id., col. 11, 61-63. It then responds by reading or writing data over the bus lines BusData[0:7] while the Ad-drValid bus line remains set to zero to indicate that data, and not another request packet, are being transmitted on the bus. Id. c. The Clocking Scheme — External and Internal Clock Signals As a memory device gets faster, i.e., as the time between signals decreases (or, as the frequency of the system increases), the time a signal takes to propagate down the bus becomes significant compared to the time between signals. This error created by the time it takes for the signal to travel can disrupt the ability of the memory devices to operate synchronously with each other. The specification discloses one way of minimizing this error by having each device receive two clock signals. Id., col. 18, 11. 63-66. The device can then use the two external clock signals to derive an internal device clock. Id. If every device uses the external clock signals to derive the same internal clock signal, each device’s internal clock can reflect a true system clock shared by all devices, despite the devices being in different positions on the bus. Id. Figure 8a shows the preferred embodiment of the clocking scheme devised by Drs. Farmwald and Horowitz. The clock generator (CLK) sends an early clock signal along the bus’s CLOCK1 line, where the signal first contacts Chip 0 and later contacts Chip N. Id., col. 19, 11. 3-7. The clock signal then loops around on a second line (the CLOCKS bus line), where it now contacts Chip N first, then contacts Chip O. Id., col. 19, 11. 7-10. An alternative embodiment uses only one bus clock line and leaves the end of the clock line unterminated, allowing the clock signal to reflect back when it reaches the end of the clock line. Id., col. 19, 11. 10-13. The reflected clock signal performs the same function as the CLOCKS signal in the preferred embodiment while remaining confined to the same clock line. Id. Figure 8b depicts the method used by each memory device to derive an internal clock signal from the two external clock signals. Figure 8a’s example shows that Chip 0 is closer to the clock generator. Chip 0 therefore receives the clock signal on CLOCK 1 before Chip N, as demonstrated by comparing when each chip detects an increase in voltage on CLOCK 1 (represented by the solid black line, 55). See id., col. 9, 11. 14-32. Meanwhile, Chip N is closer to the source of CLOCK2 than Chip O. Therefore, Chip N receives the second clock signal, CL0CK2, earlier than Chip O. Id. CLOCKS is shown in Figure 8b by the dashed line, 56. If each memory device is connected to the bus’s clock signal lines properly, the average of the times at which each chip receives CL0CK1 and CL0CK2 should be identical. In Figure 8b, this is shown as the dashed vertical line labeled 59. Thus, despite the propagation delay caused by each device being placed at a different point on the bus, each device can use two external clock signals to derive an internal clock signal that is the same in every device. Figure 8b demonstrates another feature of Drs. Farmwald and Horowitz’s invention, namely, the use of both edges of the clock signal (also referred to as the rising and falling edges of the clock signal) to gain twice the amount of information out of a single period of the clock signal. See id., col. 9,11. 33M4. As discussed, the two chips on the bus use the transition of the two clock signals from low to high to derive the midpoint depicted by the dashed line 59. The two chips also detect when each clock signal decreases, i.e., goes from high to low, as shown at 57 (CL0CK1) and 58 (CL0CK2). Each chip can calculate the midpoint of the two decreases in the two clock signals, shown by the dashed vertical line 60. As with the prior midpoint, the two chips are connected to the clock signal lines so that the midpoint measured by Chip N is the same as the midpoint measured by Chip O. By using the midpoint of the rise and fall of the two clock signals, the devices on the bus can respond at two different points in time for each period of the clock signal. Thus, the bus data frequency can be twice the clock signal frequency. See id. d. The Clocking Scheme — Responding to Internal Clock Signals The preceding discussion omits some of the complex details required to compensate for the lag between the internal clock signal and the device’s interaction with the other bus lines. To begin, a device requires both input and output circuitry for responding to signals from the bus. The input circuitry includes an “input sampler” for measuring the voltage on the bus lines and detecting an incoming signal. See id., col. 22, 11. 21-35. The output circuitry contains an “output driver” for putting data onto the bus. See id., col. 22,11.1-20. For example, the input sampler has a slight delay between when it receives a clock signal and its sampling of the bus’s data lines. Because of the system’s high frequency, it is important to minimize any such delay. Id., col. 22,11. 50-56. Figure 12 reveals that omitted complexity. The first thing to recognize is the inputs for the first clock signal (early clock, or CLOCK1) and second clock signal (late clock, or CLOCK2). The connections between the device and the bus’s clock lines are labeled CLK1 (100) and CLK2 (110). To help orient Figure 12 within the context of the prior discussion, the edited excerpt of Figure 8a below needs to be referenced. All of the circuitry shown in Figure 12 exists in each device attached to the bus. The first element of the circuit is a DC amplifier (102), which is necessary for converting the bus clock line’s relatively low voltage signal into a more powerful signal that the device can more readily recognize. See id., col. 22, 11. 60-61. The amplified clock signal then feeds into a variable delay line (103), which in turn feeds three different delay lines (104, 105, and 106). Id., col. 22, 11. 61-66. The first delay line (104) has a fixed delay time. Id. The second delay line (105) has the same fixed delay time plus a second variable delay time. Id. The third delay line (106) has the same fixed delay as the prior two lines plus a variable delay time that is half of delay line 105’s second variable delay time. Id. In Figure 12, the fixed delay time is represented as T0 and the second variable time is represented as X. The third delay line’s delay time equals the midpoint of the delay times of the first and second delay lines. The outputs of the first two delay lines (104 and 105) are labeled 107 and 108. Id., col. 22,11. 66-67. These outputs connect to the clocked input receivers on each of the two bus clock lines labeled as 101 and 111. Id., col. 22, 1. 66-col. 28, 1. 4. To be clear, these input receivers receive two signals: the external clock signal from the bus’s clock line and the internal delay signal. See id., col. 23, 11. 2-4 & Fig. 11. The clocked receivers then run feedback lines (115,116) back into the variable delay lines (103, 105). Id., col. 23,11. 3-7. The timing diagram in Figure 13 assists in understanding the purpose of all of this circuitry. As with Figure 8b, the unlabeled x-axis is time and the unlabeled y-axes of the graphs in Figure 13 are the voltage levels on the various lines. For context, labels 121 and 123 correspond to the falling edges of the first and second, or early and late, bus clocks. Id., col. 23,11. 7-13. When properly calibrated, delay lines 107 and 108 output signals similar to the early and late bus clocks respectively, but shifted early by a slight amount (128). Id., col. 23, 11. 3-13. This slight amount (128) is ideally equal to the delay time before the input sampler can respond to the clock signal and sample the bus’s data lines. Id. As discussed, the third delay line has a fixed delay time and half of the variable delay time of the second delay line. This puts the output of the third delay line (also known as the internal clock signal 73) at the midpoint of the other two delay lines. Id., col. 23, 11. 13-18. This is simply the distance labeled 129 between the internal clock signal’s falling edge (73) and the two internal delay lines’ falling edges (labeled 120 and 122). This final output is the device’s derived internal clock signal, which precedes the true midpoint of the two bus clocks by a small amount of time equal to the delay in the input sampler’s operation. In the preferred embodiment, the device also generates an inverse of the internal clock signal, referred to as the complementary internal clock signal and labeled 74 in Figure 13. To complete the story, the device has two internal clock signals that mirror each other. Each precedes the true midpoint of the bus clock signals by an amount of time equal to the delay in operating the input sampler. The preferred embodiment then harnesses half of the input samplers to one clock signal and has them sample the bus on the clock signal’s falling edge, while the other half of the input samplers sample the bus on the complement’s falling edge. Id., col. 23, 11. 26-34. In such a fashion, the device successfully samples the bus for data at the midpoint of the two external clock signals’ rising and falling edges. B. Prosecution History 1. The Original 11-Way Restriction Requirement As mentioned, Drs. Farmwald and Horowitz filed their original patent application no. 07/510,898 with 150 claims on April 18,1990. The PTO responded with a restriction requirement, forcing Drs. Farmwald and Horowitz to separate their claims into 11 distinct applications. See Detre Deck, Ex. A. The examiner defined a first group of claims (Group I, covering claims 1^15 and 56-72) as the combination of “a memory and bus subsystem including address registers, transceivers, and memory sections” and a “general mention of memory control.” Id. at 3. He then proceeded to distinguish other groups of claims as follows: Group Original claims Basis for distinction_Source II 46-55 Group I related to memory control generally. Group Id. at 3. II claims “a specific memory control and arbitration _scheme.”_ III 73-81 Group I related to timing generally. Group III claims Id. at 4. _“a specific clocking and timing scheme.”_ IV_82-90_Group IV claimed “an unrelated DRAM device.”_Id. at 1. V 91-94 Group V claimed “an unrelated semiconductor Id. at 1. _package.”_ VI 95-105 Group VI claimed “a semiconductor device and connec- See id. tion means” and generally mentioned “bus characteris- at 4-5. tics.” The examiner did not find a “combination/sub-combination” relationship between Group I and Group VI. VII 106,107 Group VI made only “a general mention of bus charae- Id. at 5. teristics.” Group VII claimed “specific bus character-_istics.”_ VIII 108-110 Group VI generally mentioned “timing and clocking.” Id. at 6. Group VIII included “specific clocking and timing con-_siderations.”_ IX 111-113 Group VI generally mentioned “storage.” Group IX Id. at 6. _included “specific receiving and storage means.”_ X 114-123 Group VI generally mentioned “I/O.” Group X related Id. at 7. _to “a specific I/O and multiplexing scheme.”_ XI 124-150 Group VI generally mentioned “input and output.” Id. at 8. Group XI related to “a specific input/output scheme using packets.” In laying out the details of the original restriction requirement, the court recognizes its limited evidentiary significance. First, the examiner purportedly distinguished claims going to separate inventions. This clearly distinguished groups IV and V from the other inventions. What is unclear is the relationship, if any, between Group I and Group VI. The examiner used the same shorthand to refer to both groups as the combination A and subcombination B br, jointly “AB br.” Yet he defined the meaning of “A” differently for Group I and Group VI. For Group I, “A” represented “a memory and bus subsystem including address registers, transceivers, and memory sections.” For Group VI, “A” represented “a semiconductor device and connection means.” Because it appears that Group I and Group VI claim different inventions, it seems that the additional prosecution history of each is of little relevance to the other. Second, the examiner divided claims to a combination and a subcombination into distinct groups where (1) “the combination as claimed does not require the particulars of the subcombination as claimed for patenta-bility” and (2) the subcombination has utility by itself. See, e.g., id. at 3. This is how the examiner distinguished groups II and III from group I and groups VII through XI from group VI. The examiner found the first requirement met whenever the sub-combination’s details appeared in a dependent claim. See id. Because all of the claims were assumed to be patentable, the presence of the subcombination in a dependent claim was evidence that the combination did not require the subcombination for the combination to be patentable. See id. To be clear, the examiner’s restriction is not evidence that each separate group is supported by the specification and separately patentable. It is only evidence that the claims, as drafted, were directed at separate inventions. Accord Honeywell Int’l., Inc. v. ITT Industries, Inc., 452 F.3d 1312, 1319 (Fed.Cir.2006) (assigning little weight to restriction requirement that did not construe claim terms or consider the specification). 2. Additional Restrictions All of the patents-in-suit (and the vast majority of the Farmwald/Horowitz patent family) descend from Group I. Group I’s prosecution history is rife with additional restrictions. One in particular is worth noting. On June 5, 1997, the examiner issued a restriction requirement for application no. 08/798,520 distinguishing claims to “a semiconductor device having at least one access-time register” and claims to “a memory device having a plurality of conductors being multiplexed for sequentially receiving an address.” The examiner noted that the two groups of claims do not require each other and would require separate prior art searches. In response, Ram-bus elected to proceed with the claims to a semiconductor device with an access-time register. II. PRIOR CLAIM CONSTRUCTION ORDERS The Farmwald/Horowitz family of patents have been previously construed in various cases involving Rambus. Certain claim terms — “integrated circuit device,” “read request,” “write request,” “transaction request” and “bus” — have been construed by the Federal Circuit. Rambus Inc. v. Infineon Techs. AG, 318 F.3d 1081, 1089-95 (Fed.Cir.2003). This court construed additional terms in a previous case between Rambus and Hynix. Hynix Semiconductor Inc. v. Rambus Inc., C-00-20905-RMW, 2004 WL 2610012 (N.D.Cal. Nov.15, 2004) (Hynix I). The Manufacturers acknowledge these prior decisions, but argue about the amount of deference owed to them. A. Stare Decisis and the Infineon Decision In Markman v. Westview Instruments, Inc., the Supreme Court cited with approval authority that treated claim construction as a question of law, not fact, and held that claim construction is exclusively the responsibility of the court. 517 U.S. 370, 116 S.Ct. 1384, 134 L.Ed.2d 577 (1996). The issue for the Court was whether the Seventh Amendment requires a jury to construe a patent. See id. at 372, 116 S.Ct. 1384. Because history and precedent provided no clear answer, the Court examined “functional considerations” to determine the scope of the Seventh Amendment’s right to a jury trial See id. at 388, 116 S.Ct. 1384. The Court held that a judge, not a jury, would be better suited to interpret a patent as a written document, in part because jurors remain “unburdened by training in exegesis.” Id. at 388-89, 116 S.Ct. 1384. The Court also noted that a jury’s ability to evaluate testimony would not be as helpful as a judge’s ability to parse a complex document. Id. 389-90, 116 S.Ct. 1384. The Markman Court buttressed its holding that functional considerations compel assigning claim construction to the court by emphasizing the “importance of uniformity in the treatment of a given patent.” Id. at 390, 116 S.Ct. 1384. The Court pointed out that issue preclusion cannot impose uniformity on infringement defendants who were not a party to a prior action. Id. at 391, 116 S.Ct. 1384 (citing Blonder-Tongue Laboratories, Inc. v. University of Ill. Foundation, 402 U.S. 313, 91 S.Ct. 1434, 28 L.Ed.2d 788 (1971)). After noting the difficulty of ensuring uniformity through issue preclusion, the Court stated that “treating interpretive issues as purely legal will promote (though it will not guarantee) intrajurisdictional certainty through the application of stare decisis on those questions not yet subject to interjurisdic-tional uniformity under the authority of the single appeals court.” Id. Since Markman, courts have treated this discussion as granting stare decisis effect to the Federal Circuit’s claim constructions. E.g., Key Pharmaceuticals v. Hercon Laboratories Corp., 161 F.3d 709, 716 (Fed.Cir.1998) (“We do not take our task lightly in this regard, as we recognize the national stare decisis effect that this court’s decisions on claim construction have.”); Hynix I, 2004 WL 2610012, at *4; Wang Laboratories, Inc. v. Oki Electric Industry Co., Ltd., 15 F.Supp.2d 166, 176 (D.Mass.1998). A district court must apply the Federal Circuit’s claim construction even where a non-party to the initial litigation would like to present new arguments. E.g., Wang Laboratories, 15 F.Supp.2d at 176 (applying the Federal Circuit’s prior claim construction to a non-party whose motion to intervene as amicus at the Federal Circuit had been denied). Here Hynix, Micron, Nanya, and Samsung — none of whom were parties to the Infineon proceedings — ask this court to deviate from the Federal Circuit’s claim construction in Infineon. The Manufacturers do not dispute that stare decisis applies to a claim construction order generally. Instead, the Manufacturers suggest that a court may depart from binding precedent where the legal basis for the prior ruling has been sufficiently eroded. The Manufacturers quote the First Circuit for the principle that “stare decisis is neither a straightjacket nor an immutable rule; it leaves room for courts to balance their respect for precedent against insights gleaned from new developments, and to make informed judgments as to whether earlier decisions retain preclusive force.” Carpenters Local Union No. 26 v. U.S. Fidelity & Guar. Co., 215 F.3d 136, 142 (1st Cir.2000). The Manufacturers argue that the Federal Circuit’s recent cases on claim construction have altered the inquiry so much that this court should not follow Infineon. In urging this court to “not follow outdated decisions,” the Manufacturers overlook a fundamental principle of stare decisis: only the court that issued the decision in question can elect not to follow it. See State Oil Co. v. Khan, 522 U.S. 3, 20, 118 S.Ct. 275, 139 L.Ed.2d 199 (1997) (“[I]t is this Court’s prerogative alone to overrule one of its precedents.”). The Federal Circuit recently illustrated this deference in Independent Ink, Inc. v. Illinois Tool Works, Inc., a case where the criticism of the existing precedent was overwhelming. See 396 F.3d 1342, 1349-51 (Fed.Cir.2005), rev’d by Illinois Tool Works Inc. v. Independent Ink, Inc., 547 U.S. 28, 126 S.Ct. 1281, 164 L.Ed.2d 26 (2006). Nonetheless, the Federal Circuit abided by “the duty of a court of appeals to follow the precedents of the Supreme Court until the Court itself chooses to expressly overrule them.” Id. at 1351. This duty applies with equal force to this court and its relationship to the Federal Circuit. The Manufacturers argue that the Phillips case has so altered claim construction that the Federal Circuit would have decided Infineon differently had it heard the case today. The court does not read Phillips as working so great a change. See Phillips v. AWH Corp., 415 F.3d 1303, 1330 (Fed.Cir.2005) (Mayer, J., dissenting) (“Again today we vainly attempt to establish standards by which this court will interpret claims. But after proposing no fewer than seven questions, ... we say nothing new, but merely restate what has become the practice over the last ten years.”). Nonetheless, it cannot entertain that question because Phillips did not overrule Infineon or change the rules of claim construction such that Infineon’s constructions need to be revisited. Accordingly, the court adopts the Federal Circuit’s construction of “integrated circuit device,” “read request,” “write request,” “transaction request” and “bus” from Infineon. For ease of reference, the court reproduces these constructions below: Claim term_Construction_Citation_ “integrated circuit A circuit constructed on a single monolithic 318 F.3d at 1091. device”_substrate, commonly called a ‘chip.’_ “read request” A series of bits used to request a read of data Id. at 1093. from a memory device where the request _identifies what type of read to perform._ “write request” A series of bits used to request a write of data to Id. at 1093. _a memory device._ “transaction request” A series of bits used to request performance of a Id. at 1093. _transaction with a memory device._ “bus” A set of signal lines to which a number of devices Id. at 1095. are connected, and over which information is transferred between devices. In applying the Infineon claim construction, the court is sensitive to the fact that three of the Manufacturers have never been heard on this subject. Their arguments seeking to interpret terms in the claims such that the alleged inventions are limited to use with the inventors’ narrow, multiplexed bus architecture has appeal, and if the court were construing the claim language on a clean slate, it might well so limit the claims. However, the slate is not clean. The Federal Circuit reviewed the intrinsic evidence and concluded that “[a]l-though some of Rambus’s claimed inventions require a multiplexing bus, multiplexing is not a requirement in all of Rambus’s claims.” Infineon, 318 F.3d at 1094. This court cannot, no matter how appealing, contradict the Infineon claim construction. B. Stare Decisis and the Hynix I Decision The parties next dispute how much deference this court owes to its prior claim construction in the earlier Hynix proceedings. The Markman Court commented that treating claim construction as a matter of law would “promote (though it will not guarantee) intrajurisdietional certainty through the application of stare decisis on those questions not yet subject to interjurisdictional uniformity under the authority of the single appeals court.” 517 U.S. at 391, 116 S.Ct. 1384. The Court’s reference to promoting, but not guaranteeing, “intra-jurisdictional certainty” suggests that a district court should follow another court’s claim construction, though it does not have to. Since Markman, various district courts have taken slightly different approaches to other courts’ claim constructions, but despite the Court’s suggestion, none has applied stare decisis. One court held that “considerable deference should be given to those prior decisions unless overruled or undermined by subsequent legal developments, including intervening case law.” Sears Petroleum & Transport Corp. v. Archer Daniels Midland Co., 2007 WL 2156251, at *8 (N.D.N.Y.2007). It then proceeded to consider arguments that it had not heard during the prior claim construction. Id. at *12. Similarly, another court held that it would defer to its prior claim construction, but only “to the extent the parties do not raise new arguments.” KX Industries, L.P. v. PUR Water Purification Products, Inc., 108 F.Supp.2d 380, 387 (D.Del.2000). Another court feared that refusing to consider a new party’s claim construction arguments raised due process concerns and therefore granted the party’s request for a Markman hearing. Texas Instruments, Inc. v. Linear Technologies Corp., 182 F.Supp.2d 580, 589-90 (E.D.Tex.2002). Meanwhile, courts in this district have been willing to consider a prior claim construction, but have stressed the importance of conducting an independent inquiry. Visto Corp. v. Sproqit Techs., Inc., 445 F.Supp.2d 1104, 1108-09 (N.D.Cal.2006) (Chen, M.J.); see also Townshend Intellectual Property, L.L.C v. Broadcom Corp., 2008 WL 171039 (N.D.Cal. Jan.18, 2008) (Fogel, J.) (modifying prior claim construction in light of a new party’s arguments). This general practice accords with the insight that a fresh look at a claim construction can hone a prior court’s understanding and construction of a patent. See e.g., Finisar Corp. v. DirecTV Group, Inc., 523 F.3d 1323, 1329 (Fed.Cir.2008). Indeed, the Federal Circuit has said that it “would be remiss to overlook another district court’s construction of the same claim terms in the same patent as part of [a] separate appeal.” Id. In Finisar, the Federal Circuit found a second district court’s claim interpretation particularly helpful where it referred back to the prior construction and noted where it disagreed. Id. The lesson from Finisar is that additional litigation can refíne and sharpen the courts’ understanding of an invention and that a second court should not defer to a prior court’s claim construction without questioning its accuracy. On the other hand, this practice appears to conflict with the Supreme Court’s understanding of stare decisis. The Supreme Court has stated that “[c]onsiderations in favor of stare decisis are at their acme in cases involving property and contract rights, where reliance interests are involved.” Payne v. Tennessee, 501 U.S. 808, 828, 111 S.Ct. 2597, 115 L.Ed.2d 720 (1991). As early as 1851, the Supreme Court explained in dictum that “stare deci-sis is the safe and established rule of judicial policy, and should always be adhered to” when dealing with cases establishing rules of property. The Genesee Chief v. Fitzhugh, 53 U.S. 443, 458, 12 How. 443, 13 L.Ed. 1058 (1851). The Court applied similar thinking in Minnesota Mining Co. v. National Mining Co., 70 U.S. 332, 3 Wall. 332, 18 L.Ed. 42 (1865), to reject a repeated attempt to litigate the possession of an estate. The Court reasoned that rules of property engender reliance, and that changing such rules damages any interests that have grown up based on those rules. Id. at 334. Contemplating the issue of mistaken decisions, the Court mused that “[djoubtful questions on subjects of this nature, when once decided, should be considered no longer doubtful or subject to change.” Id. Such firmness would discourage parties from “speculat[ing] on a change of the law” and free the courts from “the infliction of repeated arguments by obstinate litigants, challenging the justice of [the court’s] well-considered and solemn judgments.” Id. “Stare decisis is usually the wise policy, because in most matters it is more important that the applicable rule of law be settled than that it be settled right.” Burnet v. Coronado Oil & Gas Co., 285 U.S. 393, 406, 52 S.Ct. 443, 76 L.Ed. 815 (1932) (Brandeis, J., dissenting). However, the prevailing notion among the district courts and the Finisar court is that it is better to get a claim construction right than it is to get a claim construction settled. Why so many courts have intuitively reached this conclusion is not immediately clear. It may stem, however, from the imperfect analogy between a patent right and other property rights, or from the difficulty of construing complex technical terms without the benefit of the arguments of parties not involved at the time of the first construction. In explaining when to apply stare decisis, Justice Brandéis stressed that it should apply “even where the error is a matter of serious concern, provided correction can be had by legislation.” Burnet, 285 U.S. at 406, 52 S.Ct. 443. Unlike a common law rule of contract or property, a patent interpretation cannot be readily narrowed by a statute. It is doubtful Congress would take the time to do such a thing, and doing so could raise Fifth Amendment concerns. When approaching stare decisis from the perspective of what institution could best fix a mistaken interpretation, a court rather than the legislature is probably in a better position to do so. The Supreme Court has emphasized that “legislatures may alter or change their laws, without injury, as they affect the future only; but where courts vacillate and overrule their own decisions on the construction of statutes affecting the title to real property, their decisions are retrospective and may affect titles purchased on the faith of their stability.” Minnesota Mining Co., 70 U.S. at 334, 3 Wall. 332. This basis for stare decisis reflects concerns about society’s reliance on a rule of law and the harm associated with upsetting society’s expectations. See Payne, 501 U.S. at 828, 111 S.Ct. 2597 (modulating the impact of stare decisis based on the weight of reliance interests). It is unclear how many people develop reliance interests in any given claim construction. At its grandest, a claim construction could shape an entire industry’s research and development efforts (by leading people to avoid research in an area already patented) and licensing relationships (by leading people to take licenses or buy a favorably construed patent), as well as various company’s stock prices (the patent holder’s could increase on a favorable claim construction while an infringing firm’s might collapse). But this is rather speculative, and even at its greatest, a claim construction does not engender the same scope of reliance on property rights that animated the Court’s holding in United States v. Title Insurance & Trust, 265 U.S. 472, 44 S.Ct. 621, 68 L.Ed. 1110 (1924), where a reversal would have redistributed huge tracts of land overnight. While a change in the scope of a patent may dry up a royalty stream, it would not lead to eject-ments and repossessions. Thus, while “most” matters benefit from being settled rather than being settled right, claim construction appears to be an exception, at least as among district courts. Further, since the constructions in Hynix I are not final, the court is free to revisit them. Accordingly, this court will initially treat its prior construction as correct, but consider the Manufacturers’ arguments as to why a construction in Hynix I should be modified. C. Collateral Estoppel as to Hynix Putting aside Micron, Nanya, and Samsung, Rambus argues that Hynix should be precluded from challenging the court’s prior claim construction. Preclusion does not attach lightly. As stated by the Ninth Circuit, a court’s decision only bars relitigation of an issue where: (1) the issue necessarily decided at the previous proceeding is identical to the one which is sought to be relitigated; (2) the first proceeding ended with a final judgment on the merits; and (3) the party against whom collateral estoppel is asserted was a party or in privity with a party at the first proceeding. Hydranautics v. FilmTec Corp., 204 F.3d 880, 885 (9th Cir.2000); see also Kourtis v. Cameron, 419 F.3d 989 (9th Cir.2005). Rambus points out that a court has precluded a party from relitigating claim construction in situations where there appears to have not been a final judgment. E.g., TM Patents, L.P. v. Int’l Bus. Machines Corp., 72 F.Supp.2d 370, 376-80 (S.D.N.Y.1999). The prior action in TM Patents ended during trial when the parties settled. Id. at 375. Nonetheless, the court in the second action precluded TM Patents from relitigating the prior court’s claim construction because it held that the decision was sufficiently “final.” Id. at 375-76 (citing Lummus Co. v. Commonwealth Oil Ref. Co., 297 F.2d 80, 89 (2d Cir.1961)). Indeed, the law of issue preclusion uses an unusual definition of “final judgment,” namely, any adjudication that is “sufficiently firm” to be accorded preclusive effect. Luben Industries, Inc. v. United States, 707 F.2d 1037, 1040 (9th Cir.1983); see also Rest.2d of Judgments § 13. Still, the court is unpersuaded that its Hynix I claim construction order is “sufficiently firm” to grant it preclusive effect. There has not yet been a final judgment in the earlier proceedings, preventing Hynix from obtaining appellate review of this court’s claim construction. The inability to obtain appellate review bars the application of issue preclusion. Matter of Lockard, 884 F.2d 1171, 1176 (9th Cir.1989) (citing Rest.2d of Judgment § 28(1)). While the claim construction in TM Patents also could not be appealed, that was caused by the patentee’s decision to settle, not because the law prevented appellate review. See Rest.2d of Judgments § 28, cmt. a (noting that 28(1) “applies only when review is precluded as a matter of law. It does not apply in cases where review is available but is not sought.”). Because Hynix has not yet been able to exercise its right to appeal this court’s prior claim construction, it cannot be precluded from continuing to litigate the scope of Rambus’s patent claims. III. CLAIM CONSTRUCTION The parties dispute the construction of a number of terms and so focused their arguments on groups of terms. After briefly addressing the claim construction legal standard, the court’s inquiry follows the parties’ groupings of the disputes. A. Claim Construction Legal Standard The court begins its claim construction inquiry by considering the ordinary and customary meaning of the terms in the claims from the perspective of a person of ordinary skill in the art. Phillips, 415 F.3d at 1312-13. This ordinary meaning is influenced by the use of language in the asserted and unasserted claims in the patents. Id. at 1314-15. For example, the phrase “steel baffles” implies that a “baffle” need not be made of steel. See id. at 1314. More generally, the appearance of a limitation in a dependent claim creates a presumption that the independent claim lacks that limitation. Id. at 1315; but see Curtiss-Wright Flow Control Corp. v. Velan, Inc., 438 F.3d 1374, 1380-81 (Fed.Cir.2006) (discussing limits of claim differentiation). This “objective baseline” of ordinary meaning is also formed in part by the patents’ specification’s use of the claim language because a person of ordinary skill understands a claim’s language in the context of the entire patent. Id. at 1313. For example, the specification is often helpful in defining the scope of technical terms. See id. at 1315. The specification can also reveal a “special definition” of a claim term or demonstrate “an intentional disclaimer” or “disavowal” of claim scope. Id. at 1316. The specification’s statutory role in determining a claim’s validity justifies placing this heavy weight on it. Id. at 1315-16. Similarly, the prosecution history of a patent can inform the proper construction of a patent’s claims. Id. at 1317. It provides evidence of how both the Patent Office and the inventor understood the claims. Id. The prosecution history’s back-and-forth nature often makes it unclear, however, and therefore it is rarely as helpful in construing a patent’s claims as the claims themselves and the specification. Id. Still, the prosecution history can be invaluable for demonstrating the inventor’s understanding of the claims and checking “whether the inventor limited the invention in the course of prosecution, making the claim scope narrower than it would otherwise be.” Id. Finally, a court may consider extrinsic evidence like inventor and expert testimony, dictionaries, and treatises. Id. at 1318. Such evidence can be helpful, but courts must be mindful that it is not necessarily created contemporaneously with the patent application and that the litigation context can produce biased evidence. Id. Accordingly, extrinsic evidence is rarely more probative of the proper construction of the claims than the intrinsic record, id. at 1319, but extrinsic evidence is particularly helpful “[w]hen the intrinsic evidence is silent as to the plain meaning of a term.” Helmsderfer v. Bobrick Washroom Equipment, Inc., 527 F.3d 1379, 1381-83 (Fed.Cir.2008) (construing a claim term in light of three dictionary definitions); see also Phillips, 415 F.3d at 1322-23. Nonetheless, to avoid “the risk of systematic over-breadth” the court begins its inquiry focused “on how the patentee used the claim term in the claims, specification, and prosecution history, rather than starting with a broad definition and whittling it down.” Phillips, 415 F.3d at 1321. All four sources of evidence discussed above have their advantages and drawbacks and varying amounts of persuasive force. All of the sources are appropriately considered, and contrary to Samsung’s argument at the claim construction hearing, there is no “rigid algorithm” or “sequence of steps” which the court must follow. Id. at 1324. All that matters “is for the court to attach the appropriate weight to be assigned to those sources in light of the statutes and policies that inform patent law.” Id. B. The “Device” Terms and Multiplexing The first dispute between the parties is whether Rambus’s claims should be limited to DRAMs that use multiplexed bus data lines. This dispute touches on the construction of “bus” from Infineon and influences the construction of “device” and variants of “device.” Rambus argues that there is no need to construe the term “device” in isolation, but that the court should adopt the Infineon court’s construction of “integrated circuit device” and the construction of “memory device” from Hynix I. The Manufacturers proffer a detailed and limited construction of the term “device,” which they then incorporate into their proposed constructions of “integrated circuit device” and “memory device.” The proposed constructions appear below: Claim term: Rambus’s construction: The Manufacturers’ Construction: “device” (no separate construction) Electronic circuits or components with a bus interface that is adapted to connect to a multiplexed set of signal lines, each for carrying address, data, and control information, that has substantially fewer connections to signal lines than the number of bits in a single address, and that does not connect to a sepa-_rate device select line._ “integrated A circuit constructed on a A device that includes one or more integrated circuit single monolithic substrate, circuits. device”_commonly called a “chip.”_ “memory An integrated circuit device A device in which information can be stored device” in which information can be and retrieved electronically, stored and retrieved electronically. 1. “Device” At bottom, the Manufacturers’ proposed construction of “device” is an attempt to evade the Federal Circuit’s Infineon construction of the terms “integrated circuit device” and “bus.” The Manufacturers’ proposed construction of device, when incorporated into the phrase integrated circuit device, conflicts with the Federal Circuit’s construction of that phrase, which lacks the narrow, multiplexed bus limitation of the Manufacturers’ proffered construction. See Infineon, 318 F.3d at 1089-91. The Manufacturer’s construction of “device” also imports a multiplexing limitation into every claim, an interpretation the Federal Circuit already considered and rejected when it construed the term “bus.” Id. at 1094-95. The court also rejected any attempt to read a multiplexing limitation into other claim terms when it held that “multiplexing, if necessitated by the claims, is applicable to the construction of the term ‘bus,’ not ‘read request.’ ” Id. at 1093. Hynix previously made this argument regarding the construction of “device,” and the court rejected it because “[t]his end result, a multiplexed bus as part of the claim limitations, was rejected by the Federal Circuit.” Hynix I, 2004 WL 2610012, at *6. The Manufacturers argue that the court should ignore the Federal Circuit’s interpretation of “bus” because the claims-in-suit do not use the term. From this, the Manufacturers argue that the Federal Circuit’s interpretation of “bus” should not influence the interpretation of “device” because “bus” is not in dispute. Even if the term “bus” were not in dispute here, the court cannot ignore the Federal Circuit’s construction of the term because this court cannot construe a claim to blatantly conflict with the Federal Circuit’s prior interpretation. See Hynix I, 2004 WL 2610012, at *6. Nor is the court necessarily persuaded that the Manufacturers’ construction of “device” is correct, even if the court could ignore the Infineon claim construction. The Manufacturers’ construction of “device” would import a host of limitations, specifically that the device (1) be adapted to connect to a multiplexed set of signal lines, (2) have substantially fewer connections to signal lines than the number of bits in a single address, and (3) lack a separate device s